EIT-EMS-546-L-4 - Embedded Processor Labor
Tuesday, 14:00 - 18:00 Uhr, 12/274
Thursday, 14:00 - 18:00 Uhr, 12/274
Content of this lab are the modeling and extension of a typical RISC processor architecture (DLX). Students must realize the concepts of modern processor architectures (e.g. forwarding or memory caches) in hardware (synthesizable VHDL models) and analyze the runtime performance of processors. Furthermore students acquire skills in hardware validation and use of typical EDA tools (e.g. synthesis and virtual platforms) in large projects.
This lab is a „Wahlpflichtveranstaltung“ for „Vertiefungsrichtung Informationsverarbeitung (INV)“ and „Vertiefungsrichtung Eingebettete Systeme (ESY)“. Students should attend the lecture „Architektur digitaler Systeme I (85-571)“ before the lab. This lab is hold by the research group of Prof. Wehn
The lab takes place every summer semester. Registration for the lab is from start of summer semester (1th of April) up to the end of the first week with lectures; i.e. 01.04.2018 to 15.04.2018 (12:00).
Registration for this lab is done via OLAT. Access code is EPL2018.
Lab dates are on Tuesday or Thursday from 14:00 to 18:00. A meeting for detailed agreement of dates and organization (e.g. grouping) is held on Tuesday (17.04.2018 at 14:00) in the second lecture week in room 12-270.
Slides of kick-off-meeting on 25.04.2017 can be found here.
The lab consists of four exercises (numbered from 4 to 7):
- Task 4: Modeling of the pipeline stage for instruction decode (ID) of DLX in VHDL
Download Task 4
Download Hinweise zu den Quelldateien
- Task 5: Extension of the DLX-RISC-pipeline by a pipeline-Controller for hazard avoiding
Download Task 5
- Task 6E: Virtual Platforms
Download Task 6E
- Task 7_E: Virtual Platforms
Download Task 7E
- Additional Lab 4_B (only for students also registered to Lab Mikroelektronik Vertiefung)
- Additional Lab 5_B (only for students also registered to Lab Mikroelektronik Vertiefung)
- Architektur digitaler Systeme I (85-571)
- VHDL Kenntnisse