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EIT-EMS-546-L-4 - Embedded Processor Labor

Link to KIS system

Dates

Lab   
Tuesday, 14:00 - 18:00 Uhr,    12/274
Thursday, 14:00 - 18:00 Uhr,    12/274

Involved staff

Lecturer: Dipl.-Math. Uwe Wasenmüller
Assistant: Dipl.-Ing. Matthias Jung, Eng. Éder Zulian

Organisation

Content of this lab are the modeling and extension of a typical RISC processor architecture (DLX). Students must realize the concepts of modern processor architectures (e.g. forwarding or memory caches) in hardware (synthesizable VHDL models) and analyze the runtime performance of processors. Furthermore students acquire skills in hardware validation and use of typical EDA tools (e.g. synthesis and virtual platforms) in large projects.

This lab is a „Wahlpflichtveranstaltung“ for „Vertiefungsrichtung Informationsverarbeitung (INV)“ and „Vertiefungsrichtung Eingebettete Systeme (ESY)“. Students should attend the lecture „Architektur digitaler Systeme I (85-571)“ before the lab. This lab is hold by the research group of Prof. Wehn

The lab takes place every summer semester. Registration for the lab is from start of summer semester (1th of April) up to the end of the first week with lectures; i.e. 01.04.2017 to 21.04.2017 (12:00).

Registration for this lab is done via OLAT. Access code is EPL17.

Grouping can be found here.

Lab dates are on Tuesday or Thursday from 14:00 to 18:00. A meeting for detailed agreement of dates and organization (e.g. grouping) is held on Tuesday (25.04.2017 at 14:00) in the second lecture week in room 12/270.

Slides of kick-off-meeting on 25.04.2017 can be found here.

Content

The lab consists of four exercises (numbered from 4 to 7):

  • Additional Lab 4_B (only for students also registered to Lab Mikroelektronik Vertiefung)
    Download
  • Additional Lab 5_B (only for students also registered to Lab Mikroelektronik Vertiefung)
    Download

Prerequisites

  • Architektur digitaler Systeme I (85-571)
  • VHDL Kenntnisse

Remarks

ECTS-Points: 3