Link to KIS system
Monday, 14:00 - 16:30 Uhr, 12-524
Tuesday, 11:45 - 13:15 Uhr, 13-222
Tuesday, 14:00 - 16:30 Uhr, 12-524
Thursday, 15:30 - 17:45 Uhr, 12-524
Lecturer: Dipl.-Math. Uwe Wasenmüller
Involved assistants: Dr.-Ing. Christian Weis
Qualification for registration to this lab is prior participation in lecture "Grundlagen der Informationsverarbeitung" (85-314 and EIT-EIS-314-V-2 respectively). Objective of this lab is to make practical exercises of the lecture contents. To fullfill this, an introduction to the hardware description language VHDL is given; this takes place on Tuesdays in 13-222. Base knowledge is provided to specify the base components of digital logic in VHDL. Furthermore the designed circuits must be verified by simulation and will be synthesized to FPGA devices. Laboratory equipment for task preparation can be used from Monday to Friday.
VHDL content: simulation model, data types and operations, essential language constructs, synthetizable models (combinational and clocked processes), functional verification with test bench.
Please read also the explanations in the clause Remarks below.
Six exercises have to be carried out. The exercises for winter semester 2016/17 will be uploaded to the OLAT system in November / December 2016.
- Task 1: VHDL-Simulation model and first own coded models
- Task 2: Modeling of combinational circuits and usage of test benches
- Task 3: Modeling of sequential circuits and usage of test benches
- Task 4: Realization of a trafic light controller; Validation; Synthesis; place and route
- Task 5: Design of Finite State Machines; Evaluation of different modeling styles; Validation; Synthesis
- Task 6: Design of a circuit for blind signal to noise estimation; Validation; Synthesis
Will be announced in lectures
Content of Grundlagen der Informationsverarbeitung (85-314 and EIT-EIS-314-V-2 respectively)
Laboratory in 12-524 is available Monday, and Wednesday to Friday. On Tuesday equipment in 12-274 can be used. Official dates for this lab are on Monday or Tuesday from 14:00 to 16:30 or Thursday from 15:30 to 17:45. At these dates the acceptance tests will be carried out. Furthermore on Tuesdays from 11:45 to 13:15 an introduction course to VHDL is given in 13-222. This introduction course contains app. 7 lecture units; first lecture unit will be given on 8.11.2016. Documents for the Lab will be provided in this lecture on 8.11.16.
Registration for this lab will be enabled on 4.10.2016 and registration will end in the first lecture week on friday (28.10.2016 at noon).
Registration is possible via OLAT starting 4.10.2015. Please register to one of the given groups.
Groups with a maximum of 3 participants are offered. This registration does not replace a registration in the "Prüfungsamt", which is need for some study courses.
Exercises of the Lab must be prepared completely before the lab date. At the lab dates only approval and testation takes place (app. 20 to 30 minutes per task). From 18.11.16 computers and tools in lab room 12-524 and 12-274 respectively can be used from Monday to Friday from 8:00 to 18:00. Advisory service hours additionally to the lab dates will be provided (time is tbd).
Further information on organization of the lab can be found here in the slides of kick-off-meeting on 08.11.2016.