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2nd Intl. Workshop on Emerging Memory Solutions

Co-located with DATE'17 conference at March 31, 2017 in Lausanne, Switzerland


Memory manufacturing, architectures, design and test were deeply investigated to face issues linked to technology scaling such as increasing static power, maximum operating frequency and the gap between logic and memory minimum voltages. Various emerging memories solutions have appeared in recent years to replace either partially or totally already existing memories with an aim to overcome both technology and design related limitations in order to answer the requirements of many different applications. The goal of this Workshop is to bring together researchers, practitioners, and others interested in this exciting and rapidly evolving field, in order to update each other on the latest state-of-the-art, exchange ideas, and discuss future challenges.


This workshop is co-located with 2017 DATE conference in Lausanne, a beautiful city in Switzerland, situated on the shores of Lake Geneva.

The Design, Automation, and Test in Europe conference and exhibition is the main European event bringing together researchers, vendors and specialists in hardware and software design, test and manufacturing of electronic circuits and systems. Friday Workshops are dedicated to emerging research and application topics. At DATE 2017, one of the Friday Workshops is devoted to Emerging Memory Solutions. This one-day event consists of a plenary keynote, regular and poster presentations, and a panel session.


  • General Chair: Christian WeisUniversity of Kaiserslautern (DE)
  • Program Chair: Bastien Giraud – CEA-LETI (FR) 
  • Panel Chair: Ian O’Connor – INL (FR) 
  • Publicity Chair: Matthias JungUniversity of Kaiserslautern (DE) 
  • Proceeding Chair: Jean-Philippe Noel – CEA-LETI (FR) 
  • Steering Committee Member: Erik Jan Marinissen – IMEC (BE) 

Topic Areas

You are invited to participate and submit your contributions to DATE 2017 Friday Workshop on Emerging Memory Solutions. The areas of interest include (but are not limited to) the following topics:

  • Volatile memory design (SRAM, DRAM, CAM, etc.)
  • Non-Volatile memory design (ReRAM, Flash, PCM, MRAM, etc.)
  • Applications of emerging devices in memories (TFETs, nanowires, etc.)
  • 3D memories (volatile and non-volatile)
  • Processing in Memory
  • Memory Application for emerging markets
  • Memory test, BIST and debug techniques
  • Applications, products and prototypes of new memories


Workshop Agenda:

Title Speaker
08:30 Opening Welcome Address Christian Weis (UNIKL)
08:35 Keynote "Tomorrow’s Memory Systems" Bruce Jacob
(Univ. Maryland)
09:15 Special Session Emerging Memory Applications Chair:
Pascal Vivet (CEA)

Narrower-purpose Computing for Efficient Near-Memory Processing Stephan Diestelhorst (ARM)

Scalable Deep-Learning with Smart Memory Cubes
Erfan Azarkhish
(University of Bologna)
10:00 Coffee Break Poster Session 1
10:30 Invited Talk “Cortical Processors and Memories”!
Paul Franzon (NCSU)
11:00 Panel "Can We Jump over the Memory Wall with Near- or In-Memory Computing?"
Ian O'Connor (ECL)

Ahmed Hemani (KTH)
Elisa Vianello (CEA-Leti)
Francky Catthoor (IMEC)
Jean-Francois Roy (UPMEM)
Said Hamdioui (TU Delft)

12:00 Lunch Break

13:00 Keynote "Energy-Efficient Processing and Why the Memory Matters"
Borivoje Nikolić
(UC Berkeley)
13:30 Special Session SRAMs and their potential Replacements
Bastien Giraud (CEA)

Pushing the limits: challenges of low-voltage
operation in ULL High Density (HD) SRAM
Lorenzo Ciampolini (STM)

Evaluation of ternary computing approaches with NVM technologies Dietmar Fey (FAU)

Resistive RAM-Centric Computing: Design and Modeling Methodology Haitong Li (Stanford)
14:30 Coffee Break Poster Session 2
15:00 Special
Emerging RRAMs and MRAMs
Said Hamdioui (TU Delft)

SOT-MRAM : an energy efficient cache
memory alternative
Marc Drouard (Antaios)

Majority-based Synthesis for RRAM-based
in-memory computing
Pierre-Emmanuel Gaillardon (University of Utah)

An overview of Normally-off MCU based on hybrid NVM/CMOS circuits
Jean-Michel Portal (IM2NP)
16:00 Paper Session Open Call Paper Session Chair:
Matthias Jung (UNIKL)

Ultra-Low Power and Compact TFET Multibit Latch and its Applications for Low Voltage Applications Navneet Gupta (CEA)

MAGPIE: System-level Evaluation of Manycore Systems with Emerging Memory Technologies Florent Bruguier (LIRMM)
16:50 Closing

Keynote and Invited Talk Speakers

Prof. Bruce Jacob:

Bruce Jacob is a Keystone Professor of Electrical and Computer Engineering and former Director of Computer Engineering at the University of Maryland in College Park. He received the AB degree in mathematics from Harvard University in 1988 and the MS and PhD degrees in CSE from the University of Michigan in Ann Arbor in 1995 and 1997, respectively. He holds several patents in the design of circuits for electric guitars and started a company around them. He also worked for two successful startup companies in the Boston area: Boston Technology and Priority Call Management. At Priority Call Management he was the initial system architect and chief engineer. He is a recipient of a US National Science Foundation CAREER award for his work on DRAM, and he is the lead author of an absurdly large book on the topic of memory systems. His research interests include system architectures, memory systems, operating systems, and electric guitars.

Prof. Borivoje Nikolić:

Borivoje Nikolić is the National Semiconductor Distinguished Professor of Engineering at the University of California, Berkeley. He received the Dipl.Ing. and M.Sc. degrees in electrical engineering from the University of Belgrade, Serbia, in 1992 and 1994, respectively, and the Ph.D. degree from the University of California at Davis in 1999.

His research activities include digital, analog and RF integrated circuit design and communications and signal processing systems. He is co-author of the book Digital Integrated Circuits: A Design Perspective, 2nd ed, Prentice-Hall, 2003. Dr. Nikolić received many awards in his career, including the NSF CAREER award in 2003, and the best paper awards at the IEEE International Solid- State Circuits Conference, Symposium on VLSI Circuits, IEEE International SOI Conference, European Solid-State Circuits Research Conference, European Solid-State Device Research Conference, S3S conference and the ACM/IEEE International Symposium of Low- Power Electronics.


Prof. Paul D. Franzon:

Paul D. Franzon is currently the Cirrus Logic Distinguished Professor of Electrical and Computer Engineering at North Carolina State University. He earned his Ph.D. from the University of Adelaide, Adelaide, Australia in 1988. He has also worked at AT&T Bell Laboratories, DSTO Australia, Australia Telecom and three companies he cofounded, Communica, LightSpin Technologies and Polymer Braille Inc. His current interests center on the technology and design of complex microsystems incorporating VLSI, MEMS, advanced packaging and nano-electronics. He has lead several major efforts and published over 200 papers in these areas. In 1993 he received an NSF Young Investigators Award, in 2001 was selected to join the NCSU Academy of Outstanding Teachers, in 2003, selected as a Distinguished Alumni Professor, and received the Alcoa Research Award in 2005. He served with the Australian Army Reserve for 13 years as an Infantry Solider and Officer. He is a Fellow of the IEEE.

Poster List:

A Non-Volatile Flip-Flop Using Memristive Voltage Divider
Author: Mehrdad Biglari, FAU, DE
In-Memory Computation of Transitive Closure
Author: Alvaro Velasquez, University of Central Florida, US
A Scalable Near-Data Processing Simulator
Author: Geraldo Francisco de Oliveira Junior, Universidade Federal do Rio Grande do Sul, BR
4. Disruptive 3D Technology: Recent Advances on COOLCUBE(TM)
Author: Mèlanie Brocard, CEA-Leti, FR
300 MM & 200 MM Advanced Memory Platform and MPW Shuttle at LETI
Author: Elisa Vianello, CEA-Leti, FR
4T SRAM Bitcell in 3D CoolCube Technology Exploiting Dynamic Back Biasing
Author: Réda Boumchedda, CEA-Leti, FR