Division of Microelectronic Systems Design (EMS)

Eng. Éder Ferreira Zulian


Address

Erwin-Schrödinger-Straße
Building 12, Room 251
67663 Kaiserslautern

Contact

Phone: (+49) 631 / 205-5918
Fax: (+49) 631 / 205-4437
Email: zulian(at)eit.uni-kl.de

Research Areas

  • DRAM Simulation
  • Error Correction (ECC)
  • Photonic Interconnects

Publications

Access-Aware Per-Bank DRAM Refresh for Reduced DRAM Refresh Overhead
É. F. Zulian, C. Weis, N. Wehn. Accepted for publication, IEEE International Symposium on Circuits & Systems (ISCAS), May, 2020, Seville, Spain.

System Simulation with PULP Virtual Platform and SystemC
É. F. Zulian, G. Haugou, C. Weis, M. Jung, N. Wehn. International Conference on High-Performance and Embedded Architectures and Compilers (HiPEAC), Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools (RAPIDO), January, 2020, Bologna, Italy.

The Role of Memories in Transprecision Computing
C. Weis, M. Jung, É. F. Zulian, C. Sudarshan, D. M. Mathew, N. Wehn. IEEE International Symposium on Circuits and Systems (ISCAS), May, 2018, Florence, Italy.

Using gem5 for Memory Research
É. F. Zulian, M. Jung, N. Wehn. Invited talk, International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), Learning gem5 Tutorial (Gem5), March, 2018, Williamsburg, VA, USA.
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Using Run-Time Reverse-Engineering to Optimize DRAM Refresh
D. M. Mathew, É. F. Zulian, M. Jung, K. Kraft, C. Weis, B. Jacob, N. Wehn. International Symposium on Memory Systems (MEMSYS 2017), October, 2017, Washington, DC, USA.

A Bank-Wise DRAM Power Model for System Simulations
D. M. Mathew, É. F. Zulian, S. Kannoth, M. Jung, C. Weis, N. Wehn. International Conference on High-Performance and Embedded Architectures and Compilers 2017 (HiPEAC), Workshop on: Rapid Simulation and Performance Evaluation: Methods and Tools (RAPIDO), January, 2017, Stockholm, Sweden.

A New Bank Sensitive DRAMPower Model for Efficient Design Space Exploration
M. Jung, D. M. Mathew, É. F. Zulian, C. Weis, N. Wehn. International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS 2016), September, 2016, Bremen, Germany.
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Omitting Refresh - A Case Study for Commodity and Wide I/O DRAMs
M. Jung, É. F. Zulian, D. M. Mathew, M. Herrmann, C. Brugger, C. Weis, N. Wehn. 1st International Symposium on Memory Systems (MEMSYS 2015), October, 2015, Washington, DC, USA.

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