Division of Microelectronic Systems Design (EMS)

Lukas Steiner, M.Sc.


Address

Erwin-Schrödinger-Straße
Building 12, Room 224
67663 Kaiserslautern

Contact

Phone: (+49) 631 / 205-3837
Fax: (+49) 631 / 205-4437
Email: lsteiner(at)eit.uni-kl.de

Research Areas

  • Emerging Memory Standards

Publications

An LPDDR4 Safety Model for Automotive Applications
L. Steiner, D. Uecker, M. Jung, K. Kraft, M. Huonker, N. Wehn. ACM/IEEE International Symposium on Memory Systems (MEMSYS 2021), October, 2021, Washington, DC, USA.

A Novel DRAM Architecture for Improved Bandwidth Utilization and Latency Reduction Using Dual-Page Operation
C. Sudarshan, L. Steiner, M. Jung, J. Lappas, C. Weis, N. Wehn. IEEE International Symposium on Circuits and Systems (ISCAS), May, 2021, Daegu, South Korea. Published in: IEEE Transactions on Circuits and Systems II: Express Briefs (Volume: 68, Issue: 5, May 2021).

Exploration of DDR5 with the Open Source Simulator DRAMSys
L. Steiner, M. Jung, N. Wehn. 24. Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, March, 2021, Munich, Germany.

DRAMSys4.0: A Fast and Cycle-Accurate SystemC/TLM-Based DRAM Simulator
L. Steiner, M. Jung, F. S. Prado, K. Bykov, N. Wehn. International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS), July, 2020, Samos Island, Greece.

Fast and Accurate DRAM Simulation: Can we Further Accelerate it?
J. Feldmann, M. Jung, K. Kraft, L. Steiner, N. Wehn. IEEE Conference Design, Automation and Test in Europe (DATE), March, 2020, Grenoble, France.
Nominated for Best Paper Award

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