Division of Microelectronic Systems Design (EMS)

Muhammad Mohsin Ghaffar, M.Sc.


Address

Erwin-Schrödinger-Straße
Building 12, Room 264
67663 Kaiserslautern

Contact

Phone: (+49) 631 / 205-3354
Fax: (+49) 631 / 205-4437
Email: ghaffar(at)eit.uni-kl.de

Research Areas

  • 3D-DRAM integration
  • DRAM architectures
  • Memory controller

Publications

iDocChip - A Configurable Hardware Architecture for Historical Document Image Processing: Text Line Extraction
M. Tekleyohannes, V. Rybalkin, S. S. Bukhari, M. M. Ghaffar, N. Wehn and A. Dengel. Accepted for publication, International Conference on Reconfigurable Computing and FPGAs (ReConFig 2019), December, 2019, Cancun, Mexico.

iDocChip - A Configurable Hardware Architecture for Historical Document Image Processing: Multiresolution Morphology-based Text and Image Segmentation
M. Tekleyohannes, V. Rybalkin, S. Bukhari, M. M. Ghaffar, J. Varela, N. Wehn, A. Dengel. International Embedded Systems Symposium (IESS 2019), September, 2019, Friedrichshafen, Germany.
Best Paper Award

Fast Simulation of DRAMs with Neural Networks
M. Jung, J. Feldmann, M. M. Ghaffar, N. Wehn. Talk at the 1st ACM/IEEE Workshop on Machine Learning for CAD (MLCAD), September, 2019, Canmore, Alberta, Canada.

An In-DRAM Neural Network Processing Engine
C. Sudarshan, J. Lappas, M. M. Ghaffar, V. Rybalkin, C. Weis, M. Jung, N. Wehn. IEEE International Symposium on Circuits and Systems (ISCAS), May, 2019, Sapporo, Japan.

FINN-L: Library Extensions and Design Trade-off Analysis for Variable Precision LSTM Networks on FPGAs
V. Rybalkin, A. Pappalardo, M. M. Ghaffar, G. Gambardella, N. Wehn, M. Blott. 28th International Conference on Field Programmable Logic and Applications (FPL), August, 2018, Dublin, Ireland.

iDocChip: A Configurable Hardware Architecture for Historical Document Image Processing: Percentile Based Binarization
V. Rybalkin, S. S. Bukhari, A. Ghafoor, M. M. Ghaffar, N. Wehn, A. Dengel. ACM DocEng 2018 Conference, August, 2018, Halifax, Nova Scotia, Canada.

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