Division of Microelectronic Systems Design (EMS)

Vladimir Rybalkin, M.Sc.


Address

Erwin-Schrödinger-Straße
Building 12, Room 245
67663 Kaiserslautern

Contact

Phone: (+49) 631 / 205-5452
Fax: (+49) 631 / 205-4437
Email: rybalkin(at)eit.uni-kl.de

Publications

Efficient Hardware Architectures for 1D- and MD-LSTM Networks
V. Rybalkin, C. Sudarshan, C. Weis, J. Lappas, N. Wehn, L. Cheng. Accepted for publication, Springer "Journal of Signal Processing Systems", 2020.

Real-Time Energy Efficient Hand Pose Estimation: Case Study
R. Al Koutayni, V. Rybalkin, J. Malik, A. Elhayek, C. Weis, G. Reis, N. Wehn, D. Stricker. Sensors Journal, Volume 20, Issue 10, May, 2020.

When massive GPU parallelism ain't enough: A Novel Hardware Architecture of 2D-LSTM Neural Network
V. Rybalkin, N. Wehn. ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, February, 2020, Seaside, CA, USA.

iDocChip - A Configurable Hardware Architecture for Historical Document Image Processing: Text Line Extraction
M. Tekleyohannes, V. Rybalkin, S. S. Bukhari, M. M. Ghaffar, N. Wehn and A. Dengel. International Conference on Reconfigurable Computing and FPGAs (ReConFig 2019), December, 2019, Cancun, Mexico.

iDocChip - A Configurable Hardware Architecture for Historical Document Image Processing: Multiresolution Morphology-based Text and Image Segmentation
M. Tekleyohannes, V. Rybalkin, S. Bukhari, M. M. Ghaffar, J. Varela, N. Wehn, A. Dengel. International Embedded Systems Symposium (IESS 2019), September, 2019, Friedrichshafen, Germany.
Best Paper Award

An In-DRAM Neural Network Processing Engine
C. Sudarshan, J. Lappas, M. M. Ghaffar, V. Rybalkin, C. Weis, M. Jung, N. Wehn. IEEE International Symposium on Circuits and Systems (ISCAS), May, 2019, Sapporo, Japan.

FINN-L: Library Extensions and Design Trade-off Analysis for Variable Precision LSTM Networks on FPGAs
V. Rybalkin, A. Pappalardo, M. M. Ghaffar, G. Gambardella, N. Wehn, M. Blott. 28th International Conference on Field Programmable Logic and Applications (FPL), August, 2018, Dublin, Ireland.

iDocChip: A Configurable Hardware Architecture for Historical Document Image Processing: Percentile Based Binarization
V. Rybalkin, S. S. Bukhari, A. Ghafoor, M. M. Ghaffar, N. Wehn, A. Dengel. ACM DocEng 2018 Conference, August, 2018, Halifax, Nova Scotia, Canada.

Hardware Architecture of Bidirectional Long Short-Term Memory Neural Network for Optical Character Recognition
V. Rybalkin, M. R. Yousefi, N. Wehn, D. Stricker. IEEE Conference Design, Automation and Test in Europe (DATE), March, 2017, Lausanne, Switzerland.

A new Architecture for High Speed, Low Latency NB-LDPC Check Node Processing for GF(256)
V. Rybalkin, P. Schläfer, N. Wehn. IEEE 83rd Vehicular Technology Conference (VTC2016-Spring), May, 2016, Nanjing, China.

A new Architecture for High Throughput, Low Latency NB-LDPC Check Node Processing
P. Schläfer, V. Rybalkin, N. Wehn, M. Alles, T. Lehnigk-Emden, E. Boutillon. IEEE International Symposium on Personal, Indoor and Mobile Radio Communications (PIMRC), August, 2015, Hong Kong, China.

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