Division of Microelectronic Systems Design (EMS)

Vacant

Design and Implementation of (LP)DDR4 DRAM Controllers and PHYs

Type of work:

Bachelor Thesis/Studienarbeit, Master Thesis/Diploma Thesis

Assignment:

This work is dedicated to the design of DRAM controllers and their corresponding PHYs (physical interfaces). First, the specifications of LPDDR4 or DDR4 DRAMs have to be studied. Second, the student can decide if she/he wants to work on the RTL part of the controller or on the Mixed-Signal part "the PHY". Then, we specify the detailed goals of the thesis, such as enhancements in the controller or prototyping on FPGA, etc. This depends also on the skills of the student.

Skills:

  • Interest in DRAM memories and hardware development (either RTL or Mixed-Signal)
  • Digital Circuit Design (VHDL or Verilog) knowledge is an advantage
  • Lectures: EMSS I+II, Embedded Processor Lab or similar

Background:

The high bandwidth demands of modern computing systems require new memory standards, such as DDR4 or LPDDR4 DRAMs. These memories are main memory of many different computing systems. In order to control and to service the transactions from the processing system a memory controller and PHY (physical interface - I/Os) for DRAMs are needed.

Supervisor:

J. Lappas, C. Sudarshan, C. Weis

Student:

 

Jahr:

2019

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