Division of Microelectronic Systems Design (EMS)

Vacant

Modelling Emerging Memories with SystemC TLM2.0


Type of study/Type of work: 

Master thesis

Assignment: 

In this work, different emerging memories should be modeled in SystemC TLM, with special phase extensions, according to the work of [1,2]. The TLM2 virtual platform methodology enables us to explore the complete design space of hybrid memories at system-level, at very fast simulation speed with precise timing accuracy.

Emerging memories are: PCM
STT-MRAM
Memristors
LPDDR4
HBM
ReRAM

Skills: 

C++, maybe SystemC basics

Background: 

[1] Matthias Jung, Christian Weis, Norbert Wehn, and Karthik Chandrasekar. TLM modelling of 3D stacked wide I/O DRAM subsystems: a virtual platform for memory controller design space exploration. RAPIDO13

[2] Matthias Jung, Christian Weis, Patrick Bertram, Gunnar Braun and Norbert Wehn. Power Modelling of 3D-Stacked Memories with TLM2.0 based Virtual Platforms. SNUG13

Supervisor: 

Matthias Jung

Zum Seitenanfang