Fachgebiet Entwurf Mikroelektronischer Systeme (EMS)

Chirag Sudarshan, M.Sc.


Anschrift

Erwin-Schrödinger-Straße
Gebäude 12, Raum 228
67663 Kaiserslautern

Kontakt

Telefon: (+49) 631 / 205-3579
Fax: (+49) 631 / 205-4437
Email: sudarshan(at)eit.uni-kl.de

Forschungsgebiete

  • Memory Controllers
  • Application Specific Memory Systems
  • Emerging Memory Technologies

Publikationen

Channel Models for Physical Unclonable Functions based on DRAM Retention Measurements
S. Müelich, S. Bitzer, C. Sudarshan, C. Weis, N. Wehn, M. Bossert, R. F. H. Fischer. XVI International Symposium "Problems of Redundancy in Information and Control Systems" (REDUNDANCY), October, 2019, Moscow, Russia.

Fast Validation of DRAM Protocols with Timed Petri Nets
M. Jung, K. Kraft, T. Soliman, C. Sudarshan, C. Weis, N. Wehn. ACM International Symposium on Memory Systems (MEMSYS 2019), October, 2019, Washington, DC, USA.
Best Paper Award

A Lean, Low Power, Low Latency DRAM Memory Controller for Transprecision Computing
C. Sudarshan, J. Lappas, C. Weis, D. M. Mathew, M. Jung, N. Wehn. International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS), July, 2019, Samos Island, Greece.

An In-DRAM Neural Network Processing Engine
C. Sudarshan, J. Lappas, M. M. Ghaffar, V. Rybalkin, C. Weis, M. Jung, N. Wehn. IEEE International Symposium on Circuits and Systems (ISCAS), May, 2019, Sapporo, Japan.

Driving Into the Memory Wall: The Role of Memory for Advanced Driver Assistance Systems and Autonomous Driving
M. Jung, S. A. McKee, C. Sudarshan, C. Dropmann, C. Weis, N. Wehn. ACM International Symposium on Memory Systems (MEMSYS 2018), October, 2018, Washington, DC, USA.

Efficient Coding Scheme for DDR4 Memory Subsystems
K. Kraft, D. M. Mathew, C. Sudarshan, M. Jung, C. Weis, N. Wehn, F. Longnos. ACM International Symposium on Memory Systems (MEMSYS 2018), October, 2018, Washington, DC, USA.
Best Paper Award

Artificial Neural Network Specific Memory Systems
C. Sudarshan. Young Researchers Symposium, June, 2018, Kaiserslautern, Germany.

The Role of Memories in Transprecision Computing
C. Weis, M. Jung, É. F. Zulian, C. Sudarshan, D. M. Mathew, N. Wehn. IEEE International Symposium on Circuits and Systems (ISCAS), May, 2018, Florence, Italy.

Improving the Error Behavior of DRAM by Exploiting its Z-Channel Property
K. Kraft, M. Jung, C. Sudarshan, D. M. Mathew, C. Weis, N. Wehn. IEEE Conference Design, Automation and Test in Europe (DATE), March, 2018, Dresden, Germany.

An Analysis on Retention Error Behavior and Power Consumption of Recent DDR4 DRAMs
D. M. Mathew, M. Schultheis, C. Rheinländer, C. Sudarshan, M. Jung, C. Weis, N. Wehn. IEEE Conference Design, Automation and Test in Europe (DATE), March, 2018, Dresden, Germany.

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