Fachgebiet Entwurf Mikroelektronischer Systeme (EMS)

Dr.-Ing. Christian Weis


Anschrift

Erwin-Schrödinger-Straße
Gebäude 12, Raum 249
67663 Kaiserslautern

Kontakt

Telefon: (+49) 631 / 205-2711
Fax: (+49) 631 / 205-4437
Email: weis(at)eit.uni-kl.de

Forschungsgebiete

  • 3D-DRAM Integration
  • DRAM und SRAM Architekturen
  • Variationen und Zuverlässigkeit von SRAMs und DRAMs
  • Memory Controller
  • Virtual Platforms

Lehrveranstaltungen

  • Entwurf Mikroelektronischer Schaltungen und Systeme II
  • Labor Digitaltechnik 1
  • Entwurf Mikroelektronischer Schaltungen und Systeme I
  • Mikroelektronik für Nichtvertiefer

Publikationen

RRAMSpec: A Design Space Exploration Framework for High Density Resistive RAM
D. M. Mathew, A. Chinazzo, C. Weis, M. Jung, B. Giraud, P. Vivet, A. Levisse, N. Wehn. Accepted for publication, IEEE International Conference on Embedded Computer Systems Architectures Modeling and Simulation (SAMOS), July, 2019, Samos Island, Greece.

An In-DRAM Neural Network Processing Engine
C. Sudarshan, J. Lappas, M. M. Ghaffar, V. Rybalkin, C. Weis, M. Jung, N. Wehn. Accepted for publication, IEEE International Symposium on Circuits and Systems (ISCAS), May, 2019, Sapporo, Japan.

3D Memories
C. Weis, M. Jung, N. Wehn. Book chapter in the Handbook of 3D Integration Vol 4, Wiley-VCH, 2016.
Link

Driving Into the Memory Wall: The Role of Memory for Advanced Driver Assistance Systems and Autonomous Driving
M. Jung, S. A. McKee, C. Sudarshan, C. Dropmann, C. Weis, N. Wehn. ACM International Symposium on Memory Systems (MEMSYS 2018), October, 2018, Washington, DC, USA.

Efficient Coding Scheme for DDR4 Memory Subsystems
K. Kraft, D. M. Mathew, C. Sudarshan, M. Jung, C. Weis, N. Wehn, F. Longnos. ACM International Symposium on Memory Systems (MEMSYS 2018), October, 2018, Washington, DC, USA.
Best Paper Award

A Reconfigurable Accelerator for Morphological Operations
M. Tekleyohannes, C. Weis, Norbert Wehn, M. Klein, M. Siegrist. IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)(RAW2018), May, 2018, Vancouver, Canada.

A Platform for Analyzing DDR3 and DDR4 DRAMs
M. Jung, D. M. Mathew, C. Rheinländer, C. Weis, N. Wehn. IEEE International Symposium on Circuits and Systems (ISCAS), May, 2018, Florence, Italy.

The Role of Memories in Transprecision Computing
C. Weis, M. Jung, É. F. Zulian, C. Sudarshan, D. M. Mathew, N. Wehn. IEEE International Symposium on Circuits and Systems (ISCAS), May, 2018, Florence, Italy.

Improving the Error Behavior of DRAM by Exploiting its Z-Channel Property
K. Kraft, M. Jung, C. Sudarshan, D. M. Mathew, C. Weis, N. Wehn. IEEE Conference Design, Automation and Test in Europe (DATE), March, 2018, Dresden, Germany.

An Analysis on Retention Error Behavior and Power Consumption of Recent DDR4 DRAMs
D. M. Mathew, M. Schultheis, C. Rheinländer, C. Sudarshan, M. Jung, C. Weis, N. Wehn. IEEE Conference Design, Automation and Test in Europe (DATE), March, 2018, Dresden, Germany.

A Memory Centric Architecture of the Link Assessment Algorithm in Large Graphs
C. Brugger, V. Grigorovici, M. Jung, C. De Schryver, C. Weis, N. Wehn, K. Zweig. IEEE Design & Test Volume 35 Number 1, January/February 2018, pp. 7–15.

Using Run-Time Reverse-Engineering to Optimize DRAM Refresh
D. M. Mathew, É. F. Zulian, M. Jung, K. Kraft, C. Weis, B. Jacob, N. Wehn. International Symposium on Memory Systems (MEMSYS 2017), October, 2017, Washington, DC, USA.

Integrating DRAM Power-Down Modes in gem5 and Quantifying their Impact
R. Jagtap, M. Jung, W. Elsasser, C. Weis, A. Hansson, N. Wehn. International Symposium on Memory Systems (MEMSYS 2017), October, 2017, Washington, DC, USA.

A Platform to Analyze DDR3 DRAM’s Power and Retention Time
M. Jung, D. M. Mathew, C. Rheinländer, C. Weis, N. Wehn. IEEE Design & Test, July, 2017.
Link

3D-Stacked Many-Core Architecture for Biological Sequence Analysis Problems
P. Liu, A. Hemani, K. Paul, C. Weis, M. Jung, N. Wehn. International Journal of Parallel Programming (IJPP), Springer, April, 2017.

An Advanced Embedded Architecture for Connected Component Analysis in Industrial Applications
M. Tekleyohannes, M. Sadri, M. Klein, M. Siegrist, C. Weis, N. Wehn. IEEE Conference Design, Automation and Test in Europe (DATE), March, 2017, Lausanne, Switzerland.

A Bank-Wise DRAM Power Model for System Simulations
D. M. Mathew, É. F. Zulian, S. Kannoth, M. Jung, C. Weis, N. Wehn. International Conference on High-Performance and Embedded Architectures and Compilers 2017 (HiPEAC), Workshop on: Rapid Simulation and Performance Evaluation: Methods and Tools (RAPIDO), January, 2017, Stockholm, Sweden.

A Customized Many-Core Hardware Acceleration Platform for Short Read Mapping Problems Using Distributed Memory Interface with 3D-stacked Architecture
P. Liu, A. Hemani, K. Paul, C. Weis, M. Jung, N. Wehn. Journal of Signal Processing Systems, Springer, 2016.
Link

DRAMSpec: A High-Level DRAM Timing, Power and Area Exploration Tool
C. Weis, A. Mutaal, O. Naji, M. Jung, A. Hansson, N. Wehn. International Journal of Parallel Programming (IJPP), Springer, 2016.
Link

ConGen: An Application Specific DRAM Memory Controller Generator
M. Jung, I. Heinrich, M. Natale, D. M. Mathew, C. Weis, S. Krumke, N. Wehn. International Symposium on Memory Systems (MEMSYS 2016), October, 2016, Washington, DC, USA.
Link

Reverse Engineering of DRAMs: Row Hammer with Crosshair
M. Jung, C. Rheinländer, C. Weis, N. Wehn. International Symposium on Memory Systems (MEMSYS 2016), October, 2016, Washington, DC, USA.
Link

A New Bank Sensitive DRAMPower Model for Efficient Design Space Exploration
M. Jung, D. M. Mathew, É. F. Zulian, C. Weis, N. Wehn. International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS 2016), September, 2016, Bremen, Germany.
PDF

Approximate Computing with Partially Unreliable Dynamic Random Access Memory: Approximate DRAM
M. Jung, D. M. Mathew, C. Weis, N. Wehn. In Proc. IEEE/ACM Design Automation Conference (DAC), June, 2016, Austin, TX, USA.

Error Resilience and Energy Efficiency: An LDPC Decoder Design Study
P. Schläfer, C. Huang, C. Schoeny, C. Weis, Y. Li, N. Wehn, L. Dolecek. IEEE Conference Design, Automation and Test in Europe (DATE), March, 2016, Dresden, Germany.

Efficient Reliability Management in SoCs - An Approximate DRAM Perspective
M. Jung, D. M. Mathew, C. Weis, N. Wehn. 21st Asia and South Pacific Design Automation Conference (ASP-DAC), Special Session: Cross-Layer Resilience: Snapshots from the Frontier of Design, January, 2016, Macao, China.

A Cross Layer Approach for Efficient Thermal Management in 3D Stacked SoCs
M. Jung, C. Weis, N. Wehn. Journal of Microelectronics Reliability, Elsevier 2015.
Link

Reliability and Thermal Challenges in 3D Integrated Embedded Systems
C. Weis, M. Jung, N. Wehn. 1st International ESWEEK Workshop on Resiliency in Embedded Electronic Systems, October, 2015, Amsterdam, The Netherlands.
Link

Omitting Refresh - A Case Study for Commodity and Wide I/O DRAMs
M. Jung, É. F. Zulian, D. M. Mathew, M. Herrmann, C. Brugger, C. Weis, N. Wehn. 1st International Symposium on Memory Systems (MEMSYS 2015), October, 2015, Washington, DC, USA.

University Of Kaiserslautern Releases DRAMSpec In Cooperation With ARM
O. Naji, C. Weis, M. Jung, N. Wehn, A. Hansson. HiPEAC info 44 (Page 9), October, 2015, www.hipeac.net.

DRAMSys: A flexible DRAM Subsystem Design Space Exploration Framework
M. Jung, C. Weis, N. Wehn. IPSJ Transactions on System LSI Design Methodology (T-SLDM), August, 2015.
Link

A High-Level DRAM Timing, Power and Area Exploration Tool
O. Naji, A. Hansson, C. Weis, M. Jung, N. Wehn. IEEE International Conference on Embedded Computer Systems Architectures Modeling and Simulation (SAMOS), July, 2015, Samos Island, Greece.
Link

A Custom Computing System for Finding Similarities in Complex Networks
C. Brugger, V. Grigorovici, M. Jung, C. Weis, C. De Schryver, K. Zweig, N. Wehn. Best Paper Award, IEEE Computer Society Annual Symposium on VLSI (ISVLSI), July, 2015, Montpellier, France.

Thermal Aspects and High-level Explorations of 3D stacked DRAMs
C. Weis, M. Jung, C. Santos, P. Vivet, O. Naji, A. Hansson, N. Wehn. IEEE Computer Society Annual Symposium on VLSI (ISVLSI), July, 2015, Montpellier, France.

A Cross Layer Reliability Approach for Efficient Thermal Management in 3D Stacked Wireless Baseband SoCs
M. Jung, C. Weis, N. Wehn. 8th International Conference on Materials for Advanced Technologies of the Materials Research Society of Singapore 2015 (ICMAT 2015) - Symposium on Reliability and Variability of Devices for Circuits and Systems (RV-DCS), June, 2015, Singapore, Singapore.

An Optimal Microarchitecture for Finding Similarities in Complex Networks Based on Optimal Memory Hierarchies
C. Brugger, V. Grigorovici, M. Jung, C. Weis, C. De Schryver, K. Zweig, N. Wehn. WIP, IEEE/ACM Design Automation Conference (DAC), June, 2015, San Francisco, CA, USA.

Application-aware Cross-Layer Reliability Analysis and Optimization
M. Glaß, H. Aliee, L. Chen, M. Ebrahimi, F. Khosravi, V. B. Kleeberger, A. Listl, D. Müller-Gritschneder, F. Oboril, U. Schlichtmann, M. B. Tahoori, J. Teich, N. Wehn, and C. Weis. it - Information Technology 57, issue 3 (2015), de Gruyter Oldenbourg, Germany, May, 2015.

Retention Time Measurements and Modelling of Bit Error Rates of WIDE-I/O DRAM in MPSoCs
C. Weis, M. Jung, P. Ehses, C. Santos, P. Vivet, S. Goossens, M. Koedam, N. Wehn. IEEE Conference Design, Automation and Test in Europe (DATE), March, 2015, Grenoble, France.

Circuit Resilience Roadmap
V. Kleeberger, C. Weis, U. Schlichtmann, N. Wehn. Chapter 7 in: Reis, Ricardo, Cao, Yu, Wirth, Gilson (Eds.): Circuit Design for Reliability, Springer, January, 2015.
p. 121-143, ISBN 978-1-4614-4078-9
Link

Optimized Active and Power-Down Mode Refresh Control in 3D-DRAMs
M. Jung, M. Sadri, C. Weis, N. Wehn, L. Benini. IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), October, 2014, Playa del Carmen, Mexico.

Exploiting Expendable Process-Margins in DRAMs for Run-Time Performance Optimization
K. Chandrasekar, S. Goossens, C. Weis, M. Koedam, B. Akesson, N. Wehn, K. Goossens. IEEE Conference Design, Automation and Test in Europe (DATE), March, 2014, Dresden.

Energy Optimization in 3D MPSoCs with Wide-I/O DRAM
M. Sadri, M. Jung, C. Weis, N. Wehn, L. Benini. IEEE Conference Design, Automation and Test in Europe (DATE), March, 2014, Dresden.
Link

Hybrid Memory Architecture for Voltage Scaling in Ultra-Low-Power Multi-Core Biomedical Processors
D. Bortolotti, A. Bartolini, C. Weis, D. Rossi, L. Benini. IEEE Conference Design, Automation and Test in Europe (DATE), March, 2014, Dresden.

Resilience Articulation Point (RAP): Cross-layer Dependability Modeling for Nanometer System-on-chip Resilience
A. Herkersdorf, V. Kleeberger, S. Nassif, U. Schlichtmann, C. Gimmler-Dumont, C. Weis, N. Wehn, et. al. Journal of Microelectronics Reliability, Volume 54, Pages 1066-1074, ISSN 0026-2714, Elsevier 2014 , February, 2014.

Energy and Performance Exploration of Accelerator Coherency Port Using Xilinx ZYNQ
M. Sadri, C. Weis, N. Wehn, L. Benini. FPGAworld 2013, September, 2013, Copenhagen / Stockholm.

A Cross-Layer Technology-Based Study of the Impact of Memory Errors on System Resilience
V. Kleeberger, C. Gimmler-Dumont, C. Weis, A. Herkersdorf, S. Nassif, U. Schlichtmann, N. Wehn, Daniel Müller-Gritschneder. IEEE Micro, Vol. 33, no. 4, pp. 46-55, July, 2013.
Link

Towards Variation-Aware System-Level Power Estimation of DRAMs: An Empirical Approach
K. Chandrasekar, C. Weis, B. Akesson, N. Wehn, K. Goossens. In Proc. IEEE/ACM Design Automation Conference (DAC), June, 2013, Austin, TX, US.
Link

Power Modelling of 3D-Stacked Memories with TLM2.0 based Virtual Platforms
M. Jung, C. Weis, P. Bertram, G. Braun, N. Wehn. Synopsys User Group Conference (SNUG), May, 2013, Munich, Germany.
PDF

Exploration and Optimization of 3-D Integrated DRAM Subsystems
C. Weis, I. Loi, L. Benini, N. Wehn. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 32, Issue 4, Pages 597 - 610, April, 2013, New York, US.
Link

Cross-Layer Dependability Modeling and Abstraction in System on Chip
A. Herkersdorf, V. Kleeberger, S. Nassif, U. Schlichtmann, C. Weis, N. Wehn, et. al. 9th IEEE Workshop on Silicon Errors in Logic - System Effects (SELSE), March, 2013, Standford University.

System and Circuit Level Power Modeling of Energy-Efficient 3D-Stacked Wide I/O DRAMs
K. Chandrasekar, C. Weis, B. Akesson, N. Wehn, K. Goossens. In Proc. IEEE Conference Design, Automation and Test in Europe (DATE), March, 2013, Grenoble, France.

TLM Modelling of 3D Stacked Wide I/O DRAM Subsystems, A Virtual Platform for Memory Controller Design Space Exploration
M. Jung, C. Weis, N. Wehn, K. Chandrasekar. International Conference on High-Performance and Embedded Architectures and Compilers 2013 (HiPEAC), Workshop on: Rapid Simulation and Performance Evaluation: Methods and Tools (RAPIDO), January, 2013, Berlin.
Published by ACM New York, 2013, USA
Link

Modelling 3D-Stacked Memories with Virtual Platforms
M. Jung, C. Weis, N. Wehn. HiPEAC info 32 (Pages 12-13), www.hipeac.net, October, 2012.
Link

A 2.15GBit/s Turbo Code Decoder for LTE Advanced Base Station Applications
T. Ilnseher, F. Kienle, C. Weis, N. Wehn. 7th International Symposium on Turbo Codes & Iterative Information Processing, August, 2012, Gothenborg, Sweden.

Design Space of Flexible Multigigabit LDPC Decoders
P. Schläfer, M. Alles, C. Weis, N. Wehn. VLSI Design, vol. 2012, 10 pages, May, 2012.
Article ID 942893
Link

A High-Performance FPGA-Based Implementation of LZSS Compression Algorithm
I. Shcherbakov, C. Weis, N. Wehn. in Proceedings of IEEE Reconfigurable Architectures Workshop, May, 2012, Shanghai, China.

An Energy Efficient DRAM Subsystem for 3D integrated SoCs
C. Weis, I. Loi, N. Wehn, L. Benini. In Proc. IEEE Conference Design, Automation and Test in Europe (DATE), March, 2012, Dresden, Germany.
Link

DRAM Selection and Configuration for Real-Time Mobile Systems
M. Gomony, C. Weis, B. Akesson, N. Wehn, K. Goossens. In Proc. IEEE Conference Design, Automation and Test in Europe (DATE), March, 2012, Dresden, Germany.
Link

ASIC Design of a Gbit/s LDPC Decoder for Iterative MIMO Systems
C. Gimmler-Dumont, F. Kienle, C. Weis, N. Wehn, M. Alles. IEEE International Conference on Computing, Networking & Communications, January, 2012, Maui, Hawaii.
Link

Bringing C++ productivity to VHDL world: from language definition to a case study
I. Shcherbakov, C. Weis, N. Wehn. Forum on specification & Design Languages (FDL-2011), September, 2011, Oldenburg, Germany.
Link

Design Space Exploration for 3D-stacked DRAMs
C. Weis, I. Loi, N. Wehn, L. Benini. In Proc. IEEE Conference Design, Automation and Test in Europe (DATE), March, 2011, Grenoble, France.
Link

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