Fachgebiet Entwurf Mikroelektronischer Systeme (EMS)

Deepak M. Mathew, M.Sc.


Anschrift

Erwin-Schrödinger-Straße
Gebäude 12, Raum 228
67663 Kaiserslautern

Kontakt

Telefon: (+49) 631 / 205-4803
Fax: (+49) 631 / 205-4437
Email: deepak(at)eit.uni-kl.de

Forschungsgebiete

  • Memory Controller Hardware
  • Hybrid Memory Systems

Publikationen

RRAMSpec: A Design Space Exploration Framework for High Density Resistive RAM
D. M. Mathew, A. Chinazzo, C. Weis, M. Jung, B. Giraud, P. Vivet, A. Levisse, N. Wehn. Accepted for publication, IEEE International Conference on Embedded Computer Systems Architectures Modeling and Simulation (SAMOS), July, 2019, Samos Island, Greece.

Efficient Coding Scheme for DDR4 Memory Subsystems
K. Kraft, D. M. Mathew, C. Sudarshan, M. Jung, C. Weis, N. Wehn, F. Longnos. ACM International Symposium on Memory Systems (MEMSYS 2018), October, 2018, Washington, DC, USA.
Best Paper Award

A Platform for Analyzing DDR3 and DDR4 DRAMs
M. Jung, D. M. Mathew, C. Rheinländer, C. Weis, N. Wehn. IEEE International Symposium on Circuits and Systems (ISCAS), May, 2018, Florence, Italy.

The Role of Memories in Transprecision Computing
C. Weis, M. Jung, É. F. Zulian, C. Sudarshan, D. M. Mathew, N. Wehn. IEEE International Symposium on Circuits and Systems (ISCAS), May, 2018, Florence, Italy.

Improving the Error Behavior of DRAM by Exploiting its Z-Channel Property
K. Kraft, M. Jung, C. Sudarshan, D. M. Mathew, C. Weis, N. Wehn. IEEE Conference Design, Automation and Test in Europe (DATE), March, 2018, Dresden, Germany.

An Analysis on Retention Error Behavior and Power Consumption of Recent DDR4 DRAMs
D. M. Mathew, M. Schultheis, C. Rheinländer, C. Sudarshan, M. Jung, C. Weis, N. Wehn. IEEE Conference Design, Automation and Test in Europe (DATE), March, 2018, Dresden, Germany.

Using Run-Time Reverse-Engineering to Optimize DRAM Refresh
D. M. Mathew, É. F. Zulian, M. Jung, K. Kraft, C. Weis, B. Jacob, N. Wehn. International Symposium on Memory Systems (MEMSYS 2017), October, 2017, Washington, DC, USA.

A Platform to Analyze DDR3 DRAM’s Power and Retention Time
M. Jung, D. M. Mathew, C. Rheinländer, C. Weis, N. Wehn. IEEE Design & Test, July, 2017.
Link

A Bank-Wise DRAM Power Model for System Simulations
D. M. Mathew, É. F. Zulian, S. Kannoth, M. Jung, C. Weis, N. Wehn. International Conference on High-Performance and Embedded Architectures and Compilers 2017 (HiPEAC), Workshop on: Rapid Simulation and Performance Evaluation: Methods and Tools (RAPIDO), January, 2017, Stockholm, Sweden.

ConGen: An Application Specific DRAM Memory Controller Generator
M. Jung, I. Heinrich, M. Natale, D. M. Mathew, C. Weis, S. Krumke, N. Wehn. International Symposium on Memory Systems (MEMSYS 2016), October, 2016, Washington, DC, USA.
Link

A New Bank Sensitive DRAMPower Model for Efficient Design Space Exploration
M. Jung, D. M. Mathew, É. F. Zulian, C. Weis, N. Wehn. International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS 2016), September, 2016, Bremen, Germany.
PDF

Approximate Computing with Partially Unreliable Dynamic Random Access Memory: Approximate DRAM
M. Jung, D. M. Mathew, C. Weis, N. Wehn. In Proc. IEEE/ACM Design Automation Conference (DAC), June, 2016, Austin, TX, USA.

Efficient Reliability Management in SoCs - An Approximate DRAM Perspective
M. Jung, D. M. Mathew, C. Weis, N. Wehn. 21st Asia and South Pacific Design Automation Conference (ASP-DAC), Special Session: Cross-Layer Resilience: Snapshots from the Frontier of Design, January, 2016, Macao, China.

Omitting Refresh - A Case Study for Commodity and Wide I/O DRAMs
M. Jung, É. F. Zulian, D. M. Mathew, M. Herrmann, C. Brugger, C. Weis, N. Wehn. 1st International Symposium on Memory Systems (MEMSYS 2015), October, 2015, Washington, DC, USA.

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