Fachgebiet Entwurf Mikroelektronischer Systeme (EMS)

Jan Lappas, M.Sc.


Gebäude 12, Raum 207
67663 Kaiserslautern


Telefon: (+49) 631 / 205-5147
Fax: (+49) 631 / 205-4437
Email: lappas(at)eit.uni-kl.de


  • Memory Controller Hardware
  • Mixed-Signal Chip Design
  • PHY Design of Recent DDR3/4 Interfaces
  • DRAM Circuit Level Models


A Novel DRAM Architecture for Improved Bandwidth Utilization and Latency Reduction Using Dual-Page Operation
C. Sudarshan, L. Steiner, M. Jung, J. Lappas, C. Weis, N. Wehn. IEEE International Symposium on Circuits and Systems (ISCAS), May, 2021, Daegu, South Korea. Published in: IEEE Transactions on Circuits and Systems II: Express Briefs (Volume: 68, Issue: 5, May 2021).

Efficient Hardware Architectures for 1D- and MD-LSTM Networks
V. Rybalkin, C. Sudarshan, C. Weis, J. Lappas, N. Wehn, L. Cheng. Springer "Journal of Signal Processing Systems", 2020.

A Lean, Low Power, Low Latency DRAM Memory Controller for Transprecision Computing
C. Sudarshan, J. Lappas, C. Weis, D. M. Mathew, M. Jung, N. Wehn. International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS), July, 2019, Samos Island, Greece.

An In-DRAM Neural Network Processing Engine
C. Sudarshan, J. Lappas, M. M. Ghaffar, V. Rybalkin, C. Weis, M. Jung, N. Wehn. IEEE International Symposium on Circuits and Systems (ISCAS), May, 2019, Sapporo, Japan.

Weitere Publikationen

A. Renner, J. Lappas, A. König, "Cell Optimization for the IISIC CMOS-Chip Serving as a Front-End for Integrated Impedance Spectroscopy", AMA Proc. of SENSOR 2015 17th Int. Conf. on Sensors and Measurement Technology, AMA Service GmbH, pp. 166-171, 2015, ISBN 978-3-9813484-8-4.

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