Fachgebiet Entwurf Mikroelektronischer Systeme (EMS)

Dr.-Ing. Matthias Jung


Kontakt Fraunhofer IESE

Fraunhofer-Platz 1
Raum B1.09
67663 Kaiserslautern

Telefon: (+49) 631 / 6800-2279
Fax: (+49) 631 / 6800-9-2279
Email: matthias.jung(at)iese.fraunhofer.de

Forschungsgebiete

  • 3D-DRAM Integration
  • Memory Controller
  • Virtual Platforms
  • (Co-)Simulation
  • Multicores / Concurrent Software Development
  • Application Specific Memory Systems

Preise und Auszeichnungen

  • Bundessieger Fokus Schülerwettbewerb 2006
  • Grant für HiPEAC 2013 by Google
  • Best Paper Award, Young Researcher Symposium 2013
  • Amar Mukherjee Best Paper Award of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI) 2015
  • HiPEAC Paper Award 2016
  • MEMSYS - Chair's Choice Best Paper Award 2016
  • MEMSYS - Most Creative Best Presentation Award 2016
  • 2018: European Design and Automation Association (EDAA) Outstanding Dissertations Award 2017
  • 3rd best lecture in the Department of Electrical and Computer Engineering of TU Kaiserslautern (WS17/18, SCVP)
  • 2018: Preis des Freundeskreises 2017 der TU Kaiserslautern für ausgezeichnete Dissertation

Lehrveranstaltungen

  • SystemC and Virtual Prototyping - SCVP (WS17, WS18)
  • Embedded Processor Labor (SS12, SS13, SS14, SS15, SS17)
  • Principles of Electrical and Computer Engineering in CVT (WS14, WS15, WS16, WS17)
  • Software Engineering for Embedded Systems (Fernstudium, DISC)
  • Seminar Mikroelektronik (SS16)
  • YouTube Channel Xilinx Zynq

Invited Talks

  • System Simulation with gem5, SystemC and other Tools. gem5 User Workshop, ARM Research Summit, September, 2017, Cambridge, UK.
  • Coupling gem5 with SystemC TLM 2.0 Virtual Platforms. gem5 User Workshop, International Symposium on Computer Architecture (ISCA), June, 2015, Portland, OR, USA.
  • Thermal and Power Aspects of MPSoCs with WIDE I/O DRAMs, D43D: The 6th Workshop on Design for 3D Silicon Integration, June 23-24, 2014, Lausanne, Switzerland

Publikationen

Fast Validation of DRAM Protocols with Timed Petri Nets
M. Jung, K. Kraft, T. Soliman, C. Sudarshan, C. Weis, N. Wehn. ACM International Symposium on Memory Systems (MEMSYS 2019), October, 2019, Washington, DC, USA.
Best Paper Award

Fast Simulation of DRAMs with Neural Networks
M. Jung, J. Feldmann, M. M. Ghaffar, N. Wehn. Talk at the 1st ACM/IEEE Workshop on Machine Learning for CAD (MLCAD), September, 2019, Canmore, Alberta, Canada.

Rapid Identification of Shared Memory in Multithreaded Embedded Systems with Static Scheduling
J. Jahić, V. Kumar, M. Jung, G. Wirrer, N. Wehn, T. Kuhn. International Workshop on Embedded Multicore Systems (ICPP-EMS 2019) in conjunction with the 48th International Conference on Parallel Processing (ICPP 2019), August, 2019, Kyoto, Japan.

A Lean, Low Power, Low Latency DRAM Memory Controller for Transprecision Computing
C. Sudarshan, J. Lappas, C. Weis, D. M. Mathew, M. Jung, N. Wehn. International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS), July, 2019, Samos Island, Greece.

RRAMSpec: A Design Space Exploration Framework for High Density Resistive RAM
D. M. Mathew, A. Chinazzo, C. Weis, M. Jung, B. Giraud, P. Vivet, A. Levisse, N. Wehn. IEEE International Conference on Embedded Computer Systems Architectures Modeling and Simulation (SAMOS), July, 2019, Samos Island, Greece.

An In-DRAM Neural Network Processing Engine
C. Sudarshan, J. Lappas, M. M. Ghaffar, V. Rybalkin, C. Weis, M. Jung, N. Wehn. IEEE International Symposium on Circuits and Systems (ISCAS), May, 2019, Sapporo, Japan.

Speculative Temporal Decoupling Using fork()
M. Jung, F. Schnicke, M. Damm, T. Kuhn, N. Wehn. IEEE Conference Design, Automation and Test in Europe (DATE), March, 2019, Florence, Italy.

3D Memories
C. Weis, M. Jung, N. Wehn. Book chapter in the Handbook of 3D Integration Vol 4, Wiley-VCH, 2019.
Link

A Framework for Non-Intrusive Trace-driven Simulation of Manycore Architectures with Dynamic Tracing Configuration
J. Jahić, M. Jung, T. Kuhn, C. Kestel, N. Wehn. RV 2018 - The 18th International Conference on Runtime Verification, November, 2018, Limassol, Cyprus.

Driving Into the Memory Wall: The Role of Memory for Advanced Driver Assistance Systems and Autonomous Driving
M. Jung, S. A. McKee, C. Sudarshan, C. Dropmann, C. Weis, N. Wehn. ACM International Symposium on Memory Systems (MEMSYS 2018), October, 2018, Washington, DC, USA.

Efficient Coding Scheme for DDR4 Memory Subsystems
K. Kraft, D. M. Mathew, C. Sudarshan, M. Jung, C. Weis, N. Wehn, F. Longnos. ACM International Symposium on Memory Systems (MEMSYS 2018), October, 2018, Washington, DC, USA.
Best Paper Award

Enabling Continuous Software Engineering for Embedded Systems Architectures with Virtual Prototypes
P. O. Antonino, M. Jung, A. Morgenstern, F. Faßnacht, T. Bauer, A. Bachorek, T. Kuhn, E. Y. Nakagawa. 12th European Conference on Software Architecture (ECSA 2018), September, 2018, Madrid, Spain.

A Model-Based Safety Analysis of Dependencies Across Abstraction Layers
C. Dropmann, E. Thaden, M. Trapp, D. Uecker, R. Amarnath, L. Avila da Silva, P. Munk, M. Schweizer, M. Jung, R. Adler. 37th International Conference on Computer Safety, Reliability and Security (SafeComp), September, 2018, Västeras, Sweden.

BOSMI: A Framework for Non-Intrusive Monitoring and Testing of Embedded Multithreaded Software on the Logical Level
J. Jahić, T. Kuhn, M. Jung, N. Wehn. IEEE International Conference on Embedded Computer Systems Architectures Modeling and Simulation (SAMOS), July, 2018, Samos Island, Greece.

A Platform for Analyzing DDR3 and DDR4 DRAMs
M. Jung, D. M. Mathew, C. Rheinländer, C. Weis, N. Wehn. IEEE International Symposium on Circuits and Systems (ISCAS), May, 2018, Florence, Italy.

The Role of Memories in Transprecision Computing
C. Weis, M. Jung, É. F. Zulian, C. Sudarshan, D. M. Mathew, N. Wehn. IEEE International Symposium on Circuits and Systems (ISCAS), May, 2018, Florence, Italy.

Using gem5 for Memory Research
É. F. Zulian, M. Jung, N. Wehn. Invited talk, International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), Learning gem5 Tutorial (Gem5), March, 2018, Williamsburg, VA, USA.
PDF

Driving Against the Memory Wall: The Role of Memory for Autonomous Driving
M. Jung, N. Wehn. Workshop on New Platforms for Future Cars: Current and Emerging Trends at IEEE Conference Design, Automation and Test in Europe (DATE), March, 2018, Dresden, Germany.

Improving the Error Behavior of DRAM by Exploiting its Z-Channel Property
K. Kraft, M. Jung, C. Sudarshan, D. M. Mathew, C. Weis, N. Wehn. IEEE Conference Design, Automation and Test in Europe (DATE), March, 2018, Dresden, Germany.

An Analysis on Retention Error Behavior and Power Consumption of Recent DDR4 DRAMs
D. M. Mathew, M. Schultheis, C. Rheinländer, C. Sudarshan, M. Jung, C. Weis, N. Wehn. IEEE Conference Design, Automation and Test in Europe (DATE), March, 2018, Dresden, Germany.

A Memory Centric Architecture of the Link Assessment Algorithm in Large Graphs
C. Brugger, V. Grigorovici, M. Jung, C. De Schryver, C. Weis, N. Wehn, K. Zweig. IEEE Design & Test Volume 35 Number 1, January/February 2018, pp. 7–15.

Using Run-Time Reverse-Engineering to Optimize DRAM Refresh
D. M. Mathew, É. F. Zulian, M. Jung, K. Kraft, C. Weis, B. Jacob, N. Wehn. International Symposium on Memory Systems (MEMSYS 2017), October, 2017, Washington, DC, USA.

Integrating DRAM Power-Down Modes in gem5 and Quantifying their Impact
R. Jagtap, M. Jung, W. Elsasser, C. Weis, A. Hansson, N. Wehn. International Symposium on Memory Systems (MEMSYS 2017), October, 2017, Washington, DC, USA.

Support Development and Testing of Concurrent Software through Supervised Software Execution
J. Jahić, T. Kuhn, M. Jung, N. Wehn. Advanced Computer Architecture and Compilation for High-Performance Embedded Systems (ACACES), July, 2017, Fiuggi, Italy.
PDF

A New State Model for DRAMs Using Petri Nets
M. Jung, K. Kraft, N. Wehn. IEEE International Conference on Embedded Computer Systems Architectures Modeling and Simulation (SAMOS), July, 2017, Samos Island, Greece.

Supervised Testing of Concurrent Software in Embedded Systems
J. Jahić, T. Kuhn, M. Jung, N. Wehn. IEEE International Conference on Embedded Computer Systems Architectures Modeling and Simulation (SAMOS), July, 2017, Samos Island, Greece.

System Simulation with gem5 and SystemC: The Keystone for Full Interoperability
C. Menard, M. Jung, J. Castrillon, N. Wehn. IEEE International Conference on Embedded Computer Systems Architectures Modeling and Simulation (SAMOS), July, 2017, Samos Island, Greece.

A Platform to Analyze DDR3 DRAM’s Power and Retention Time
M. Jung, D. M. Mathew, C. Rheinländer, C. Weis, N. Wehn. IEEE Design & Test, July, 2017.
Link

3D-Stacked Many-Core Architecture for Biological Sequence Analysis Problems
P. Liu, A. Hemani, K. Paul, C. Weis, M. Jung, N. Wehn. International Journal of Parallel Programming (IJPP), Springer, April, 2017.

A Bank-Wise DRAM Power Model for System Simulations
D. M. Mathew, É. F. Zulian, S. Kannoth, M. Jung, C. Weis, N. Wehn. International Conference on High-Performance and Embedded Architectures and Compilers 2017 (HiPEAC), Workshop on: Rapid Simulation and Performance Evaluation: Methods and Tools (RAPIDO), January, 2017, Stockholm, Sweden.

A Customized Many-Core Hardware Acceleration Platform for Short Read Mapping Problems Using Distributed Memory Interface with 3D-stacked Architecture
P. Liu, A. Hemani, K. Paul, C. Weis, M. Jung, N. Wehn. Journal of Signal Processing Systems, Springer, 2016.
Link

DRAMSpec: A High-Level DRAM Timing, Power and Area Exploration Tool
C. Weis, A. Mutaal, O. Naji, M. Jung, A. Hansson, N. Wehn. International Journal of Parallel Programming (IJPP), Springer, 2016.
Link

ConGen: An Application Specific DRAM Memory Controller Generator
M. Jung, I. Heinrich, M. Natale, D. M. Mathew, C. Weis, S. Krumke, N. Wehn. International Symposium on Memory Systems (MEMSYS 2016), October, 2016, Washington, DC, USA.
Link

Reverse Engineering of DRAMs: Row Hammer with Crosshair
M. Jung, C. Rheinländer, C. Weis, N. Wehn. International Symposium on Memory Systems (MEMSYS 2016), October, 2016, Washington, DC, USA.
Link

A New Bank Sensitive DRAMPower Model for Efficient Design Space Exploration
M. Jung, D. M. Mathew, É. F. Zulian, C. Weis, N. Wehn. International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS 2016), September, 2016, Bremen, Germany.
PDF

Exploring System Performance using Elastic Traces: Fast, Accurate and Portable
R. Jagtap, S. Diestelhorst, A. Hansson, M. Jung, N. Wehn. IEEE International Conference on Embedded Computer Systems Architectures Modeling and Simulation (SAMOS), July, 2016, Samos Island, Greece.

Approximate Computing with Partially Unreliable Dynamic Random Access Memory: Approximate DRAM
M. Jung, D. M. Mathew, C. Weis, N. Wehn. In Proc. IEEE/ACM Design Automation Conference (DAC), June, 2016, Austin, TX, USA.

Conference Report: 1st International Symposium on Memory Systems (MEMSYS’15)
M. Jung. HiPEAC info 45 (Page 13), January, 2016, www.hipeac.net.
Link

Efficient Reliability Management in SoCs - An Approximate DRAM Perspective
M. Jung, D. M. Mathew, C. Weis, N. Wehn. 21st Asia and South Pacific Design Automation Conference (ASP-DAC), Special Session: Cross-Layer Resilience: Snapshots from the Frontier of Design, January, 2016, Macao, China.

Software Architectures for Embedded Software Systems
P. Oliveira, A. Morgenstern, M. Jung, T. Kuhn, N. Wehn. Distance and Independent Studies Center (DISC) University of Kaiserslautern, 2016, Kaiserslautern, Germany.

A Cross Layer Approach for Efficient Thermal Management in 3D Stacked SoCs
M. Jung, C. Weis, N. Wehn. Journal of Microelectronics Reliability, Elsevier 2015.
Link

Reliability and Thermal Challenges in 3D Integrated Embedded Systems
C. Weis, M. Jung, N. Wehn. 1st International ESWEEK Workshop on Resiliency in Embedded Electronic Systems, October, 2015, Amsterdam, The Netherlands.
Link

Omitting Refresh - A Case Study for Commodity and Wide I/O DRAMs
M. Jung, É. F. Zulian, D. M. Mathew, M. Herrmann, C. Brugger, C. Weis, N. Wehn. 1st International Symposium on Memory Systems (MEMSYS 2015), October, 2015, Washington, DC, USA.

University Of Kaiserslautern Releases DRAMSpec In Cooperation With ARM
O. Naji, C. Weis, M. Jung, N. Wehn, A. Hansson. HiPEAC info 44 (Page 9), October, 2015, www.hipeac.net.

DRAMSys: A flexible DRAM Subsystem Design Space Exploration Framework
M. Jung, C. Weis, N. Wehn. IPSJ Transactions on System LSI Design Methodology (T-SLDM), August, 2015.
Link

A High-Level DRAM Timing, Power and Area Exploration Tool
O. Naji, A. Hansson, C. Weis, M. Jung, N. Wehn. IEEE International Conference on Embedded Computer Systems Architectures Modeling and Simulation (SAMOS), July, 2015, Samos Island, Greece.
Link

A Custom Computing System for Finding Similarities in Complex Networks
C. Brugger, V. Grigorovici, M. Jung, C. Weis, C. De Schryver, K. Zweig, N. Wehn. Best Paper Award, IEEE Computer Society Annual Symposium on VLSI (ISVLSI), July, 2015, Montpellier, France.

Thermal Aspects and High-level Explorations of 3D stacked DRAMs
C. Weis, M. Jung, C. Santos, P. Vivet, O. Naji, A. Hansson, N. Wehn. IEEE Computer Society Annual Symposium on VLSI (ISVLSI), July, 2015, Montpellier, France.

A Cross Layer Reliability Approach for Efficient Thermal Management in 3D Stacked Wireless Baseband SoCs
M. Jung, C. Weis, N. Wehn. 8th International Conference on Materials for Advanced Technologies of the Materials Research Society of Singapore 2015 (ICMAT 2015) - Symposium on Reliability and Variability of Devices for Circuits and Systems (RV-DCS), June, 2015, Singapore, Singapore.

Virtual Development on Mixed Abstraction Levels: an Agricultural Vehicle Case Study
M. Jung, T. Purusothaman, X. Pan, S. Piao, T. Kuhn, C. Grimm, K. Berns, N. Wehn. Synopsys Users Group Conference (SNUG), June, 2015, Munich, Germany.

Coupling gem5 with SystemC TLM 2.0 Virtual Platforms
M. Jung, N. Wehn. gem5 User Workshop, International Symposium on Computer Architecture (ISCA), June, 2015, Portland, OR, USA.
Link

An Optimal Microarchitecture for Finding Similarities in Complex Networks Based on Optimal Memory Hierarchies
C. Brugger, V. Grigorovici, M. Jung, C. Weis, C. De Schryver, K. Zweig, N. Wehn. WIP, IEEE/ACM Design Automation Conference (DAC), June, 2015, San Francisco, CA, USA.

Retention Time Measurements and Modelling of Bit Error Rates of WIDE-I/O DRAM in MPSoCs
C. Weis, M. Jung, P. Ehses, C. Santos, P. Vivet, S. Goossens, M. Koedam, N. Wehn. IEEE Conference Design, Automation and Test in Europe (DATE), March, 2015, Grenoble, France.

Optimized Active and Power-Down Mode Refresh Control in 3D-DRAMs
M. Jung, M. Sadri, C. Weis, N. Wehn, L. Benini. IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), October, 2014, Playa del Carmen, Mexico.

Thermal Modelling of 3D Stacked DRAM with Virtual Platforms
M. Jung, M. Sadri, N. Wehn. Advanced Computer Architecture and Compilation for High-Performance Embedded Systems, ACACES 2014, July, 2014, Fiuggi, Italy.
ISBN 978-88-905806-2-8
PDF

Energy Optimization in 3D MPSoCs with Wide-I/O DRAM
M. Sadri, M. Jung, C. Weis, N. Wehn, L. Benini. IEEE Conference Design, Automation and Test in Europe (DATE), March, 2014, Dresden.
Link

Virtual Platforms for Fast Exploration of Computing Systems in Finance
C. Brugger, M. Jung, S. Omland. Young Researcher Symposium 2013, November, 2013, Kaiserslautern.
1. Best Paper Award
Link

Virtual Platforms for Fast Memory Subsystem Exploration Using gem5 and TLM2.0
M. Jung, M. Sadri, N. Wehn. Ninth International Summer School on Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems (ACACES13), July, 2013, Fiuggi, Italy.
PDF

Virtual Platforms for Memory Controller Design Space Exploration
M. Jung, Designers Track Talk. IEEE/ACM Design Automation Conference (DAC), June, 2013, Austin, TX, USA.

TLM Modelling of 3D Stacked Wide I/O DRAM Subsystems
M. Jung, Work-in-Progress Poster Session. IEEE/ACM Design Automation Conference (DAC), June, 2013, Austin, TX, USA.

Power Modelling of 3D-Stacked Memories with TLM2.0 based Virtual Platforms
M. Jung, C. Weis, P. Bertram, G. Braun, N. Wehn. Synopsys User Group Conference (SNUG), May, 2013, Munich, Germany.
PDF

TLM Modelling of 3D Stacked Wide I/O DRAM Subsystems, A Virtual Platform for Memory Controller Design Space Exploration
M. Jung, C. Weis, N. Wehn, K. Chandrasekar. International Conference on High-Performance and Embedded Architectures and Compilers 2013 (HiPEAC), Workshop on: Rapid Simulation and Performance Evaluation: Methods and Tools (RAPIDO), January, 2013, Berlin.
Published by ACM New York, 2013, USA
Link

Modelling 3D-Stacked Memories with Virtual Platforms
M. Jung, C. Weis, N. Wehn. HiPEAC info 32 (Pages 12-13), www.hipeac.net, October, 2012.
Link

A Scalable Multi-Core ASIP Virtual Platform For Standard-Compliant Trellis Decoding
M. Jung, C. Brehm, N. Wehn. Synopsys User Group Conference (SNUG), May, 2012, Munich, Germany.
Link
PDF

Energy Efficient Acceleration and Evaluation of Financial Computations Towards Real-Time Pricing
C. De Schryver, M. Jung, N. Wehn, H. Marxen, A. Kostiuk, R. Korn. Proceedings of the 15th International Conference on Knowledge-Based and Intelligent Information & Engineering Systems (KES), pages 177-186, September, 2011, Kaiserslautern.
Link

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