Fachgebiet Entwurf Mikroelektronischer Systeme (EMS)

Vladimir Rybalkin, M.Sc.


Gebäude 12, Raum 245
67663 Kaiserslautern


Telefon: (+49) 631 / 205-5452
Fax: (+49) 631 / 205-4437
Email: rybalkin(at)eit.uni-kl.de


An In-DRAM Neural Network Processing Engine
C. Sudarshan, J. Lappas, M. M. Ghaffar, V. Rybalkin, C. Weis, M. Jung, N. Wehn. Accepted for publication, IEEE International Symposium on Circuits and Systems (ISCAS), May, 2019, Sapporo, Japan.

FINN-L: Library Extensions and Design Trade-off Analysis for Variable Precision LSTM Networks on FPGAs
V. Rybalkin, A. Pappalardo, M. M. Ghaffar, G. Gambardella, N. Wehn, M. Blott. 28th International Conference on Field Programmable Logic and Applications (FPL), August, 2018, Dublin, Ireland.

iDocChip: A Configurable Hardware Architecture for Historical Document Image Processing: Percentile Based Binarization
V. Rybalkin, S. S. Bukhari, A. Ghafoor, M. M. Ghaffar, N. Wehn, A. Dengel. ACM DocEng 2018 Conference, August, 2018, Halifax, Nova Scotia, Canada.

Hardware Architecture of Bidirectional Long Short-Term Memory Neural Network for Optical Character Recognition
V. Rybalkin, M. R. Yousefi, N. Wehn, D. Stricker. IEEE Conference Design, Automation and Test in Europe (DATE), March, 2017, Lausanne, Switzerland.

A new Architecture for High Speed, Low Latency NB-LDPC Check Node Processing for GF(256)
V. Rybalkin, P. Schläfer, N. Wehn. IEEE 83rd Vehicular Technology Conference (VTC2016-Spring), May, 2016, Nanjing, China.

A new Architecture for High Throughput, Low Latency NB-LDPC Check Node Processing
P. Schläfer, V. Rybalkin, N. Wehn, M. Alles, T. Lehnigk-Emden, E. Boutillon. IEEE International Symposium on Personal, Indoor and Mobile Radio Communications (PIMRC), August, 2015, Hong Kong, China.

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