Design and Implementation of (LP)DDR4 DRAM Controllers and PHYs
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●●●○○ Programming
●●●○○ Theory
Supervisor: J. Lappas, C. Sudarshan, C. Weis
Freie Arbeiten
Hardware Implementation and Evaluation of a Triple-Error-Correcting BCH Decoding Architecture
●●●●● Hardwaredesign
●○○○○ Programming
●●●○○ Theory
Supervisor: O. Griebel
Hardwareimplementierung eines Decoders für Polar Codes
●●●●○ Hardwaredesign
●●●○○ Programming
●●●○○ Theory
Supervisor: C. Kestel
A SystemC Visualization Tool
●●○○○ Hardwaredesign
●●●●● Programming
●○○○○ Theory
Supervisor: J. Feldmann, M. Jung
Modelling Emerging Memories with SystemC TLM2.0
●●●○○ Hardwaredesign
●●●●● Programming
●●●○○ Theory
Supervisor: M. Jung
Exploration of a new All Programmable Heterogeneous MPSoC computing platform from Xilinx (Zynq UltraScale+ EG)
●●●○○ Hardwaredesign
●●●●○ Programming
●●○○○ Theory
Supervisor: V. Rybalkin, M. Tekleyohannes