Modelling of DRAM-based PIM architecture in an open-source cycle-accurate SystemC/TLM-based DRAM simulator
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Supervisor: C. Sudarshan
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Acceleration of Simulations Using a Custom Operating System
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Supervisor: M. Jung
Formal Verification of DRAM Controllers Using Timed Petri Nets
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Supervisor: L. Steiner, C. Sudarshan, T. Ludwig
Estimation of the Roofline Model with gem5
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Supervisor: M. Jung
Design and Implementation of (LP)DDR4 DRAM Controllers and PHYs
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Supervisor: J. Lappas, C. Sudarshan, C. Weis
Hardwareimplementierung eines Decoders für Polar Codes
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Supervisor: C. Kestel
A SystemC Visualization Tool
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Supervisor: J. Feldmann, M. Jung
Modelling Emerging Memories with SystemC TLM2.0
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Supervisor: M. Jung