Hardware Implementation and Evaluation of a Triple-Error-Correcting BCH Decoding Architecture
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Supervisor: O. Griebel
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Hardwareimplementierung eines Decoders für Polar Codes
●●●●○ Hardwaredesign
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●●●○○ Theory
Supervisor: C. Kestel
Evaluation of Recurrent Neural Network based Decoders for Convolutional and Turbo Codes
○○○○○ Hardwaredesign
●●●●● Programming
●●●●○ Theory
Supervisor: S. Weithoffer
A SystemC Visualization Tool
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Supervisor: J. Feldmann, M. Jung
Investigation of Windowed Interleavers for Turbo-Codes
○○○○○ Hardwaredesign
●●●●● Programming
●●●●○ Theory
Supervisor: S. Weithoffer
Implementation of a Iteration Unrolled Turbo Decoder on FPGA
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●●●●○ Theory
Supervisor: S. Weithoffer
Modelling Emerging Memories with SystemC TLM2.0
●●●○○ Hardwaredesign
●●●●● Programming
●●●○○ Theory
Supervisor: M. Jung
Implementierung und Evaluierung von SC-Turbo-Codes
○○○○○ Hardwaredesign
●●●●● Programming
●●●●○ Theory
Supervisor: S. Weithoffer
Exploration of a new All Programmable Heterogeneous MPSoC computing platform from Xilinx (Zynq UltraScale+ EG)
●●●○○ Hardwaredesign
●●●●○ Programming
●●○○○ Theory
Supervisor: V. Rybalkin, M. Tekleyohannes