HW/SW Codesign for RISC-V based LPDDR4X-PHY Management Controller
●●●●○ Hardwaredesign
●●●●○ Programming
●●○○○ Theory
Supervisor: J. Feldmann, J. Lappas
Student: Ali Shamya
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Investigation on Layered Decoding Schedules for LDPC Codes
●○○○○ Hardwaredesign
●●●●○ Programming
●●●●○ Theory
Supervisor: M. Herrmann, O. Griebel
Student: Yazan Kazhalawi
Acceleration of a High Secure Hashing Algorithm using Near Memory Computing on a Custom RISC-V Platform
●●●●● Hardwaredesign
●●●●○ Programming
●●●○○ Theory
Supervisor: J. Feldmann, M. Schöffel
Student: Maria Feting
Formal Verification of DRAM Controllers Using Timed Petri Nets
●●●○○ Hardwaredesign
●●●●○ Programming
●●●●○ Theory
Supervisor: L. Steiner, C. Sudarshan, M. Schwarz
Student: Bryan Olmos
A Pass-Transistor-Logic Compatible Static Timing Analysis Engine for Path-based Delay Optimization
●●○○○ Hardwaredesign
●●●●○ Programming
●●●○○ Theory
Supervisor: A. Chinazzo, J. Lappas
Student: Mohamed Amine Riahi