A SystemC/TLM framework for characterizing and validating the RTL implementation of a memory controller
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Supervisor: C. Sudarshan, M. Jung
Student: Kirill Bykov
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Design and Implementation of a Blockchain-based Smart Outlet Concept
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Supervisor: F. Lauer, C. Rheinländer
Student: Daniel Gretzke
Log-MAP Approximations for Iteration Unrolled Turbo Decoders
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Supervisor: S. Weithoffer
Student: Karin Schweikert
Design and Implementation of a Hybrid Memory Controller
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Supervisor: D. M. Mathew
Student: Maxmilian Moritz Schöffel
Design of an FMC compatible eMMC adapter board for Hybrid Memory Emulations
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Supervisor: C. Rheinländer
Student: Jens Ullmert
Design of a customized transparent Gateway for IPv6-based IoT Infrastructure utilizing 6LoWPAN via Bluetooth Low Energy
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Supervisor: F. Lauer
Student: Josua Mayer
Investigation of a state metric compression technique for Turbo Decoders
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Supervisor: S. Weithoffer
Student: Yannick Mukuta Bondo
Hardware implementation of an ARP interleaver address generator
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●●○○○ Programming
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Supervisor: S. Weithoffer
Student: Safet Omerovic
Hardware implementation of a QPP interleaver address generator
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●●○○○ Programming
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Supervisor: S. Weithoffer
Student: Alexander Burkhard