Analysis and Exploration of hardware-aware Compression Techniques for Deep Neural Networks
●○○○○ Hardwaredesign
●●●●● Programming
●●●●○ Theory
Supervisor: J. Ney, V. Rybalkin, M. M. Ghaffar
Student: Stephan Stürz
Laufende Arbeiten
Design and Evaluation of a Low-Cost Infrared Camera-Based Positioning System
●●●●○ Hardwaredesign
●●●●○ Programming
●●●○○ Theory
Supervisor: F. Lauer
Student: Patrick Eckes
Systolic Array Based Quantized Neural Network Accelerator with Custom Memory Hierarchy to Minimize Off-Chip Transfers
●●●○○ Hardwaredesign
●●●●○ Programming
●○○○○ Theory
Supervisor: M. M. Ghaffar, C. Weis
Student: Rosy Elizabeth Sebastian
Power Modeling of Modern DRAM Memories
●●○○○ Hardwaredesign
●●●○○ Programming
●●●●○ Theory
Supervisor: C. Weis, M. Jung
Student: Luiza Correa
Evaluation of Quantum-Safe Digital Signature Algorithms in the Context of TLS-based Low Power IoT
●○○○○ Hardwaredesign
●●●●● Programming
●●●●○ Theory
Supervisor: M. Schöffel, F. Lauer
Student: Lucas Weber