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A Pass-Transistor-Logic Compatible Static Timing Analysis Engine for Path-based Delay Optimization
Type of work:
Bachelor Thesis
Assignment:
This work is dedicated to the semi-automatic optimization (sizing) of ptl logic cells (e.g. full adders) under different constraints:
minimum Delay
minimum Energy for specific Delay
maximum Robustness (Soft errors, Process/Voltage/Temperature variations) for specific Delay/Energy constraints
The logic cells that should be optimized are implemented in a variety of logic styles (static CMOS, Pass-transistor Logic, Transmission Gate and others). As a base the student will use a in-house developed scripting and simulation framework written in JULIA (similar to Matlab). As a logic cell he/she will use our in-house logic cell library. Detailed investigations will be performed regarding a pass transistor compatible based static timing analysis engine.
Skills:
Digital Circuit Design/Spice Simulation knowledge is an advantage
Lectures: EMSSI/MNV or similar
Basic Programming skills in MATLAB/PYTHON or JULIA
Background:
CMOS logic style
PTL logic style
Full-adder cells
Supervisor:
Student:
Mohamed Amine Riahi
Year:
2021