Fachgebiet Entwurf Mikroelektronischer Systeme (EMS)

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Investigation on Layered Decoding Schedules for LDPC Codes


●○○○○ Hardwaredesign
●●●●○ Programming
●●●●○ Theory

Type of work:

Bachelor Thesis


LDPC codes are a well-established class of Forward-Error-Correction (FEC) codes with excellent error detection and correction capabilities for large code block sizes. The irregular structure of the underlying factor graph (Tanner graph), however, limits the achievable parallelism of respective high throughput, full-parallel decoding architectures and hence the achievable throughput. Layered decoding is a method to serialize the processing of the factor graph and, at the same time, improve the convergence behavior of the decoder. In this way, parallelism on node level can be traded-off against parallelism on frame level.

In this work, different layered decoding schedules are investigated on algorithmic level with respective software simulations. The investigation comprises a comprehensive comparison between row- and column-layered schedules with different number of layers in terms of convergence behavior and implications on respective high-throughput decoder implementations.


  • C/C++/Julia Programming Language
  • Digital Hardware Design
  • Information/Coding Theory


M. Herrmann, O. Griebel


Yazan Kazhalawi



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